1. Field of the Invention
This invention relates to a device for suppressing voltage fluctuation and higher harmonics. And more particularly, in a system wherein power is supplied from a power source system to a load of large power fluctuation and harmonic current, this invention relates to a device for suppressing voltage fluctuation and higher harmonics, that suppresses the voltage fluctuation and higher harmonics of the power source system that are created by the power fluctuation of the load.
2. Description of the Related Art
Conventionally, in order to suppress the voltage fluctuations and higher harmonics of a power source system that are created by a load, such as an arc furnace, of irregular power fluctuation and large capacity, and that generates irregular higher harmonics, it has been the practice to arrange in parallel with the load a device for compensating the reactive power, negative phase sequence current and harmonic current of the load. An example is described in the specification of Japanese patent disclosure No. H3-183324 and U.S. Pat. No. 5,077,517.
FIG. 4 shows a diagrammatic circuit layout of such a conventional device for suppressing voltage fluctuation and higher harmonics. To avoid complexity, the three-phase system is shown as a single-line connection diagram.
In FIG. 4, power is supplied to a load 1 from an AC power source 2 through a transmission line 3 (let its impedance be jXS) and a receiving transformer 4 (let its impedance be jXT). A voltage fluctuation and higher harmonics suppression device constituted by a self-commutated converter 10 is arranged in parallel with load 1 and is controlled by a control circuit 30. A harmonic filter 7 is provided with the object of suppressing the higher harmonics generated by load 1 and improving the power factor. Self-commutated converter 10 is constructed, as shown in FIG. 5, by AC reactors 12, gate turn-off thyristors (GTO) 13, diodes 14, and a DC capacitor 15.
Control circuit 30 is constituted as follows. Specifically, it is equipped with: a current instruction calculation unit 31 that inputs a load current iL detected by a current transformer 5 and a system voltage V detected by a voltage detection transformer 6 and that finds a current instruction value iLo for suppressing voltage fluctuation; a harmonic current instruction calculation unit 32 that inputs a system current iS flowing in the power source system and detected by a current transformer 8 and that finds a harmonic current instruction value iHo for suppressing the higher harmonics emitted to the power source system; and an adder circuit 33 that adds current instruction values iLo and iHo. Current iC is controlled through an automatic current signal regulator (ACR) 34 and a gate circuit 35, in response to the deviation between a current iC flowing in self-commutated converter 10 detected by a current transformer 11 and a current instruction value iCo of self-commutated converter 10 arrived at by the addition process performed by this adder circuit 33.
Here, current instruction value iLo is a signal for compensating the load reactive power, but if required, a signal for compensating the negative phase sequence current of load 1 could be added.
Next, a specific example of the conventional voltage fluctuation and higher harmonics suppression device shown in FIG. 4 will be described with reference to FIG. 6. In this example, current instruction calculation unit 31 outputs a signal for compensating the negative phase sequence current of load 1 in addition to a signal for compensating the load reative power. Parts which are the same as in FIG. 4 are given the same reference numerals and a description of them is omitted.
The load current iL of load 1 detected by current transformer 5 is the line current of the three-phase circuit. A three-phase/two-phase converter circuit 31A converts this three-phase AC current to two-phase AC current. This conversion is expressed by equation (1), where iR, iS and iT are the respective line currents of three-phase AC current iL and id and iq are the two-phase AC currents. ##EQU1##
In the case of the circuit voltage, the respective phase voltages VR, VS and VT of three-phase AC voltage V detected by voltage detection transformer 6 are converted to two-phase AC voltages vd and vq by three-phase/two-phase converter circuit 31B. This conversion is expressed by equation (2) which is equivalent to that of equation (1), substituting current i by voltage v. ##EQU2##
Synchronization detection circuit 31C converts two-phase voltage signals vd, vq obtained by the two-phase conversion to synchronous voltage signals vdo, vqo, synchronized with the fundamental wave component. Reactive power detection circuit 31D respectively inputs synchronized voltage signals vdo, vqo and two-phase AC currents id, iq, and detects instantaneous real power p and instantaneous imaginary power q. That is, reative power detection circuit 31D detects so-called instantaneous real power p and instantaneous imaginary power q as defined in "Journal of the Institute of Electrical Engineers of Japan, Article No. 58-B60, P41 to 48 "Theory of Generalization of Instantaneous Reactive Power and Its Applications". These are found by the calculation of equation (3). ##EQU3##
Also, synchronous voltage signals vdo, vqo, in the two-phase AC, are orthogonal components of magnitude lpu; vd and vdo may be considered as practically equal, and vq and vqo may be considered as practically equal. Consequently, p also means the instantaneous active power supplied to load 1 from AC power source 2, while q also means the instantaneous reactive power circulating between the two phases. In this embodiment, only instantaneous reactive power q is used for calculating current instruction value iQo.
Instantaneous imaginary power (instantaneous reative power) q is input to a filter 31E, which filters it, and a load reactive power QL is thereby found. A reative power instruction value QLo is found by multiplying load reactive power QL by a compensation gain KQ (fixed value), by a coefficient circuit 31F. This is then further converted to a current instruction value iQo By supplying it to an instantaneous current calculation circuit 31G. The calculation of current instruction value iQo is performed by inverse conversion of equation (3) and equation (1). Specifically, if we assume that an instantaneous real power instruction value is po and an instantaneous imaginary current instruction value is qo, current instruction values ido and iqo in the two-phase AC current and current instruction values iRo, iSo and iTo in each line of the three-phase AC current are given by equations (4) and (5). ##EQU4##
Where, in the calculation of current instruction value iQo for the reactive power, po=o and qo=QL are substituted in equation (4).
Also, three-phase AC load current iL detected by current transformer 5 is converted to two-phase AC currents id and iq by performing the calculation of equation (1) in a three-phase/two-phase conversion circuit 31H. Two-phase AC currents id and iq are then input to a negative phase sequence power detection circuit 31J, where negative phase sequence power is detected. In this case, the calculation is performed after inverting vqo (multiplied by -1), in the calculation of the instantaneous real power and instantaneous imaginary power using equation (3).
The (-vqo) used in this calculation is obtained by inverting the polarity of output vqo of synchronous detection circuit 31C using an inverting circuit 31K. In the output of negative phase sequence power detection circuit 31J, the fundamental wave positive phase sequence power is detected as the AC power of the doubled frequency of the fundamental wave frequency, and the fundamental wave negative phase sequence power is detected as DC power, so the fundamental wave negative phase sequence powers pN and qN can be obtained by filtering the outputs of negative phase sequence power detection circuit 31J by filters 31L and 31M. Negative phase sequence power instruction values pNo, qNo are found by multiplying fundamental wave negative phase sequence powers pN, qN by a compensating gain KN (fixed value) using coefficient circuits 31N, 31P respectively. There are then input to an instantaneous current calculation circuit 31Q, where they are converted to negative phase sequence current instruction value iNo. This calculation is performed using equation (4) and equation (5), but just as described above, this is performed after multiplying vqo by -1.
A harmonic current instruction calculation unit 32 comprises a filter 32A and a coefficient circuit 32B. Current iS of the power source system detected by current transformer 8 is input to filter 32A which thereby detects a harmonic current iH. This is input to coefficient circuit 32B and multiplied by compensation gain KH (fixed value) to obtain a harmonic current instruction value iHo.
Just to make sure, harmonic current instruction calculation unit 32 is constructed with three R,S,T units corresponding to three-phase (R,S,T) components of system current iS. And, harmonic current instruction value iHo also includes three-phase (R,S,T) components.
Reactive power current instruction value iQo, negative phase sequence current instruction value iNo and harmonic current instruction value iHo found as above are combined by adder circuit 33 to obtain current instruction value iCo for self-commutated converter 10. If explained in detail, three-phase (R,S,T) components of instruction values iQo, iNo and iHo are added to obtain three-phase (R,S,T) components of instruction value iCo, respectively.
Output current iC of self-commutated converter 10 is made to track current instruction value iCo by current control performed by automatic current signal regulator 34 using the deviation between output current iC detected by current transformer 11 and current instruction value iCo found as above. The output of automatic current signal regulator 34 is input to gate circuit 35 which generates ON/OFF pulses for PWM control of self-commutated converter 10. ON/OFF pulses are then supplied to respective gates of GTOs 13 of self-commutated converter 10 shown in FIG. 5.
A steel-making arc furnace is an example of a load 1 to be compensated by the voltage fluctuation and higher harmonics suppression device described above. In such an arc furnace, reactive power, negative phase sequence current and harmonic current change irregularly with time, and their magnitudes are respectively very different depending on the condition of the material in the furnace. FIG. 7 shows an example of a fluctuation of reactive power QL of an arc furnace (including leading-phase capacity), and a voltage fluctuation .DELTA.V of the system. From this Figure, it can be seen that the range of fluctuation of the reative power is different at the commencement of melting of the material (scrap) (melting period) and after melting of the material has been fully completed (refining period). The range of fluctuation of the reactive power in the refining period, shown as QL2 in the Figure is less than one half that in the melting period, shown as QL1 in the Figure, and the range of fluctuation of the voltage is proportional to this. Though not shown in the Figure, it is found that there is the same tendency to the above regarding the negative phase sequence current and harmonic current also.
As described above, in the conventional voltage fluctuation and higher harmonics suppression device, compensation gains KQ, KN and KH used in finding respective current instruction values iQo, iNo and iHo are fixed. In order to totally compensate the reactive power, negative phase sequence current and harmonic current resulting from load fluctuation, it is necessary to take all the compensation gains as being 1, and to determine the capacity of the suppression device with reference to the amount of fluctuation in the melting period.
As a result, this capacity is determined to be fairly large. However, since the range of fluctuation in the refining period is small, there is no possibility that output of the suppression device reaches the rated capacity. If this is considered over the period of one heat cycle, although the rated capacity is fully utilized in the melting period (about one-third of the heat cycle), in the remaining period i.e. the refining period, only about one-half of the rated capacity is utilized, which is uneconomic.
Also, in general, there are no cases where both the voltage fluctuation and the higher harmonics are totally suppressed. Usually, the capacity of the suppression device of voltage fluctuation and higher harmonics is determined such as to limit these within two certain limiting values. In this case, the capacity of the voltage fluctuation and higher harmonics suppression device is smaller than the maximum amount of fluctuation such as of the reactive power in the melting period. If now we provisionally assume that the capacity of the suppression device is made one-half of the maximum amount of fluctuation of the reactive power, there is the problem that, when compensation gain KQ is 1, the current instruction value of the suppression device in the melting period will exceed the rated value. In practice, since the output of the suppression device is limited to the rated value, the suppressing effect on voltage fluctuation is adversely affected. In order to avoid this, compensation gain KQ must be made smaller than 1 (e.g. 0.5). In this case, there is the problem that, as described above, the utilization rate of the suppression device in the refining period is poor.
Although the above problems relate to the reactive power, the same could be said regarding the negative phase sequence current and harmonic current.
Also, there was the problem that, in the case where voltage fluctuation and higher harmonics are simultaneously suppressed, if the suppression device does not have the capacity to fully compensate all of the reactive power, negative phase sequence current and harmonic current, in the prior art, since, the respective compensation gains are fixed, when one or other of these components increases and reaches the rated capacity, the other components cannot be compensated.